1. Field of the Invention
The present invention pertains to the field of integrated circuit devices. More particularly, this invention relates to a random access memory having circuitry for stressing memory cells.
2. Background
A typical prior static random access memory (SRAM) comprises an array of SRAM cells. Each SRAM cell typically comprises a set of six transistors. The six transistors in a typical SRAM cell are arranged as a pair of cross coupled inverter circuits and a pair of pass gates. The pull-up transistors of the inverter circuits usually prevent leakage currents in the SRAM cell from discharging the internal data storage nodes of the SRAM cell.
Such an SRAM is typically implemented on an integrated circuit die according to a process technology that forms semiconductor and metal interconnect structures onto the integrated circuit die. Typically, the semiconductor structures include diffusion regions and polysilicon structures for the transistors in the SRAM. The metal interconnect structures typically provide electrical interconnection between the transistors and other devices in the SRAM.
Such an integrated circuit process technology typically forms a set of contacts within each SRAM cell. Such contacts include contacts formed between metal interconnect structures and contacts formed between the diffusion regions of the transistors of the SRAM cell.
Defects sometimes occur in the semiconductor and metal interconnect structures of an integrated circuit during such a manufacturing process. Such manufacturing defects can cause failures in the contacts in the SRAM cells. Such manufacturing defects can also cause failures of individual transistors in the SRAM cells. Typically, manufacturing quality testing procedures are provided to detect such defects in newly manufactured integrated circuits.
During a typical manufacturing quality test procedure, the integrated circuits are placed in a highly specialized integrated circuit tester. Such a tester usually tests an SRAM by writing a predetermined data pattern to the SRAM cells, and then immediately reading the SRAM cells to verify the stored data pattern. If the data written to the SRAM does not match the data read from the SRAM, then the integrated circuit device is usually deemed defective.
Unfortunately, such a test procedure typically does not detect manufacturing defects that cause data retention problems in the SRAM cells. For example, an SRAM cell having a defective pull-up transistor at an internal data storage node retains stored charge for only a short period of time. The charge stored at the internal nodes of such an SRAM cell usually discharges through the diffusion regions of the transistors of the SRAM cell. A defective pull-up transistor usually cannot maintain the charge level at the internal node.
One prior method for detecting such data retention defects is to provide a tester delay interval that allows such a defective SRAM cell to discharge. Such a delay interval typically occurs between the write of the test data pattern to the SRAM and the subsequent read-verify of the SRAM.
Unfortunately such tester delays significantly increase the time required for testing each integrated circuit. An increase in tester time for each integrated circuit decreases the utility of the integrated circuit device tester. Typically, such a tester can perform tests on fewer devices in a fixed time period if tester delays are added to detect data retention problems in the SRAM cells.
As a consequence, additional integrated circuit testers must typically be provided to maintain a desired tester yield with such tester delays. Unfortunately, such integrated circuit testers are extremely expensive. The extra integrated circuit testers greatly increase the overall manufacturing costs for such integrated circuit devices.